------------------------ZX81 Clock doubler-----------------------------

Rev 1.0 - 8/27/96 Kevin Baker [krbaker@edge.net]

Please refer to the accompanying .gif file for reference designators.
Reference designators are for purposes of discussion only - wiring
differences are allowable.

Background:
----------
   I have spoken with a number of people over the years who expressed
a desire to up the clock rate on the Z80 processor used in the ZX81.
BASIC (and some machine code) is a little slow on this machine. Unfortunately,
the simple (but clever!) design of the ZX81, because of cost issues, would
not allow a clock rate other than the 3.25MHz, due to the display mechanism.
The 6.5MHz clock rate is needed to output the 256 bits in a horizontal scan
line, each character (8 bits) needing to be output each 1.23uS. Because the
processor is outputting the character codes, it must fetch a new character
each 1.23us to be serially shifted out. That just happens to be the length
of a NOP instruction when the Z80 is clocked at 3.25MHz, which works out
well because a divide-by-two off of the 6.5MHz can be used to generate the
clock. Being a real-time embedded systems engineer, I can imagine there was a
lot of thought and midnight oil burned coming up with this system.For more
in-depth information on this technique, see Don Lancaster's "Cheap Video"
series of books, if still in print.
   Berated as it was, the video technique used on the ZX81 turned out to be
very versatile with some clever programming, ultimately able to display high
resolution graphics that apparently even Sir Clive thought not possible. This
would not be possible with dedicated, hard-wired video generation logic.
   So, the problem with changing the clock rate boils down to making sure
that the Z80 gets a 3.25MHz clock when it's generating video, and we can
play with the clock at other times. Of course, for SAVE and LOAD to work
with the fixed delays built into the ROM, we also need to put the normal
clock back when doing tape operations.
   When the ZX81 is executing code instead of producing the display, the
NMIs come at regular intervals, producing the blank lines at the top and
bottom automatically. Fortunately, the timing for the NMIs is controlled
by the ULA and not by the processor clock. This means we can run at whatever
speed we want and the NMIs will give us the timing necessary to get the
blank lines correctly, with the Z80 only counting the pulses so that it 
knows when to generate the active video.
   The NMI generator is the key to the functionality of the clock doubler.
Basically, when the NMIs are on, we can run at a faster rate, slowing down
only when the blank lines are done and video needs to be produced. The 
circuitry basically senses the NMI on and off 'commands', and switches the
clock rate accordingly. If we are careful, we can also run turbo in the 
FAST mode as long as we don't need a FAST display or the tape functions.
No NMIs are generated in the FAST mode, so we don't have an 'automatic'
switchover like in the SLOW mode.

Circuit operation:
-----------------

   The clock oscillator in the ULA is not TTL level compatible. We must
build an external Pierce oscillator and put the 6.5MHz crystal in it for
our master timing generation. Then we run one buffered output to the ULA
and the another into the switching circuit. This is the function of IC1a,
IC1b, and IC1c. We probably could run the Z80 at a faster rate than 6.5MHz,
but doubling the clock makes life a little simpler, since we can easily
synchronize the clock switching and we already have 6.5MHz available because
the ULA requires it. IC4a inverts the divide-by-two processor clock output
from the ULA. This is our normal clock. IC2a and IC2b give us a way to put
a high signal in and select the clock, and IC3a simply combines the two
outputs to send to the Z80. Simple, huh? Not quite. We must switch the
processor clock at a safe point in the machine cycle, and we need to sync
so that the Z80 sees a nice glitch-free clock. IC3b provides us with a low
going pulse whenever BOTH clocks are low. This 'safe' period is about 77nS
long. This signal is inverted and delayed before being buffered.  The rising
edge of the pulse is delayed something a little less than 33nS, marking
a point approx. in the center of the 'safe' period. This pulse goes to 
flip flop IC6b, allowing its output to change at the best point. This
flip flop directly controls the clock speed selects.
   IC7 is a 74HC138, which is decoding the I/O address. In order to make
the switching automatic, addresses FD and FE are used, which are the NMI
enable and disable respectively. We would like to manually switch also,
so IC4d is used at the input on A7 and A6. It responds whenever A6=A7,
and A4 and A5 are high. This gives an address range of 0011 xxxx and
1111 xxxx. A0, A1 and A3 are used to futher narrow this range for the
various controls. IC3d insures that only an I/O write will activate any
circuitry. IC8a, IC8b, and IC8c give us 4 inputs to select the slower
clock rate. It will switch off when the doubler is disabled, when a /HALT
opcodes occurs, or on a write to FD or FF. The doubler is turned on when
a write to FE occurs, which is the NMI enable.
   That really only leaves bringing up the circuit in some known fashion.
We use the /RESET signal to disable the doubler at power on. The ROM does
a check for proper NMI timing on NEW, and at the faster rate the ROM will
decide you don't even have a SLOW mode, so you are stuck with a flashing
screen. IC5a gives you a way to enable or disable switching, which is
always disabled at power up. When you enable the switching it will be done
automatically as long as you stay in the SLOW mode.

Notes:
------
IMPORTANT: Although your Z80 MAY appear to function just fine, it will not
reliably work at this clock rate. Symptoms may range from total whiteout
to working, but giving strange results for some operations, such as a floating
point number in response to a PEEK. You need to get at least an 8MHz Z80,
and a CMOS version is even better (less heat). The cost on a CMOS Z80 that
runs at 8MHz is about $5, and is available from JDR Microdevices (www.jdr.com).
The other issue is memory access time. If you have built my internal 64K RAM
upgrade, you should not experience any difficulties. I CANNOT guarantee that
this circuit will work with DRAMs (such as RAM packs). Try at your own risk,
and good luck.

When you go to the FAST mode, the normal clock is selected. When you attempt
to go to slow mode, you can't. You need to disable the auto switching, then
select SLOW. Write to port 36H to enable switching, port 37H to disable.
Also, disable before you do a NEW. The slow speed will be automatically 
selected during tape operations, but it may not be quick enough. The halt
signal also selects the slow speed because the OUT FD,A instruction comes
too late in the video process. Without the /HALT signal, the top couple of
lines are skewed. Because of IC4d, you can manually select slow/fast speed
independent of the NMI generator, except for the fact that the ULA does not
completely decode the address. There is a work around for anyone interested.
This means you could select fast clock in FAST mode with no ill effects,
at least as far as the NMI generator is concerned.
   The speed factor improvement is approx. 2.07x as fast when the doubler
is enabled (in SLOW mode).
   Now, if I can just get my hands on a 13MHz crystal....

Kevin Baker
krbaker@edge.net